The present invention relates generally to electronic circuits, and, more specifically to reducing power consumption of electronic circuits.
Electronic circuits are designed using digital logic elements including logic gates and combinational logic circuits. The digital logic elements include complementary metal-oxide semiconductor (CMOS) circuits. CMOS circuits consume power, which leads to high power dissipation and increases junction temperatures of the electronic circuits. Power dissipation is also a concern, especially for low power circuits that run on batteries because excessive power consumption reduces battery charge more quickly.
Power is usually dissipated from a circuit in the form of dynamic power and is classified as one of two types: switching power and short circuit power. Switching power is dissipated by CMOS circuits by charging and discharging various load capacitances (gate/wire/source/drain capacitances) of the transistors while switching and short circuit power is dissipated when both transistors (p-type and n-type) of a CMOS circuit remain switched ON for a short intermediate time period during transistor state changes. During this intermediate time period, current flows from supply to ground and leads to dissipation of short circuit power.
Reducing power consumption requires reducing power dissipation caused by both switching and short circuit powers. Existing techniques such as power gating and clock gating reduce power dissipation by shutting off the supply of power to digital logic elements and to clock generation and distribution circuits. However, multiple parallel applications and architectural limitations restrict the number of logic elements and clock generation and distribution circuits that can be shut down. Continuous power is therefore required by most of the logic elements.
Other conventional methods for reducing power consumption alter specific characteristics of the digital logic elements. For example, one method optimizes timing delays of the logic elements to reduce power dissipation. Another method minimizes the power dissipation based on a minimum summation of the short circuit power by altering drive strengths of digital logic elements and checking timing degradation of the entire circuit. The process of checking timing degradation is repeated for each logic element of the circuit. Yet another method alters sizes of the logic elements to reduce power dissipation. All of the above-mentioned methods alter a characteristic of a logic element and deteriorate the performance of the electronic circuit.
Therefore, it would be advantageous to have a system that reduces power consumption without impacting performance, and that overcomes the above-mentioned limitations of the conventional power reduction methods.